Scan design test techniques are frequently used to facilitate testing of complicated integrated circuit devices. A variety of these techniques are disclosed in U.S. Pat. Nos. 6,453,456 and 6,490,702. In particular, FIG. 10 of the '702 patent discloses a scan chain circuit 110 that purports to solve a latch adjacency problem when testing for delay faults within an integrated circuit. This scan chain circuit 110 includes a plurality of shift register latches 30 that operate as stages within the scan chain circuit 110. One shift register latch is illustrated as including a master latch 32a and a slave latch 34a. The output of the slave latch 34a is provided to a first input of a combinational logic device 122. This combinational logic device 122 is illustrated as a two-input AND gate. The output of the slave latch 34a is also provided to a first input of a multiplexer 112a, which is responsive to a select signal SEL. A second inverted input 116 of the multiplexer 112a also receives the output of the slave latch 34a. The output of the multiplexer 112a is provided to an input of a next shift register latch within the scan chain circuit. This next shift register latch is illustrated as including a master latch 32b and a slave latch 34b. The output of the slave latch 34b is provided to a second input of the combinational logic device 122. This combinational logic device 122 is illustrated as undergoing a conventional delay fault test by having one input of the device 122 switch low-to-high while the other input of the device 122 is held high. The timing of this low-to-high switching of the one input of the device 122 is synchronized with a leading edge of the next clock pulse (not shown). To facilitate this delay fault test, the second inverted input 116 of the multiplexer 112a is selected (i.e., SEL=0) so that the output of the next shift register latch (i.e., output of the slave latch 34b) is held at a logic 1 level when the next clock pulse is received.
Accordingly, based on the illustrated configuration of the shift register latches 30 within the scan chain circuit, a value of the select signal SEL can be used to control whether the multiplexers 112a–112c operate to pass a true or complementary version of the output of a respective slave latch 34a–34c to the next shift register latch within the scan chain circuit 110. Nonetheless, even if the output of the slave latch 34a can be controlled to switch states (i.e., switch 0→1 or 1→0) in response to the clock pulse (not shown), an output of the next shift register latch within the scan chain circuit (i.e., the output of the slave latch 34b) will nonetheless be a function of a value of the output of the preceding slave latch 34a during the delay fault test operation. This functional dependency between the output of one shift register latch and the output of a preceding shift register latch during the fault test operation can limit the effectiveness of the scan chain circuit when testing for other more complicated types of delay faults within an integrated circuit device.